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| TECHNICAL DATA IN74HC05A Hex Inverter with Open-Drain Outputs High-Performance Silicon-Gate CMOS The IN74HC05A is identical in pinout to the LS/ALS05. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device contains six independent gates, each of which performs the logic INVERT function. The open-drain outputs require external pull-up resistors for proper logical operation. They may be connected to other open-drain outputs to implement active-high wired-AND functions. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC05AN Plastic IN74HC05AD SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs A L PIN 14 =VCC PIN 7 = GND H Z = High Impedance Output Y Z L 31 IN74HC05A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 32 IN74HC05A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.0 85 C 1.5 3.15 4.2 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1.0 10 125 C 1.5 3.15 4.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1.0 40 A A Unit VIH Minimum High-Level Input Voltage Maximum Low Level Input Voltage Maximum Low-Level Output Voltage VOUT=0.1 V IOUT 20 A VOUT= VCC-0.1 V or 0.1 V IOUT 20 A VIN=VIH IOUT 20 A VIN=VIH IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOL V IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Maximum ThreeState Leakage Current VIN=VCC or GND VIN=VCC or GND IOUT=0A Output in High-Impedance State VIN= VIL or VIH IOUT= VCC or GND IOZ 6.0 0.5 5.0 10 A 33 IN74HC05A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter V Guaranteed Limit 25 C to -55C 125 24 20 75 15 13 10 10 85C 125C Unit tPLZ, tPZL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State) Power Dissipation Capacitance (Per Gate) 2.0 4.5 6.0 2.0 4.5 6.0 - 150 30 26 95 19 16 10 10 180 36 31 110 22 19 10 10 ns tTHL ns CIN COUT pF pF Typical @25C,VCC=5.0 V 8.0 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Figure 2. Test Circuit EXPANDED LOGIC DIAGRAM (1/6 of the Device) * Denotes open-drain outputs 34 |
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